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DATA SHEET
MOS INTEGRATED CIRCUIT
PD75P3018
4-BIT SINGLE-CHIP MICROCONTROLLER
The PD75P3018 replaces the PD753017's internal mask ROM with a one-time PROM, and features expanded ROM capacity. Because the PD75P3018 supports programming by users, it is suitable for use in evaluations of systems in development stages using the PD753012, 753016, or 753017, and for use in small-scale production. The following document describes further details of the functions. Please make sure to read this document before starting design. PD753017 User's Manual : U11282E
FEATURES
Compatible with PD753017 Memory capacity: * PROM : 32768 x 8 bits * RAM : 1024 x 4 bits Can operate in same power supply voltage as the mask version PD753017 * VDD = 2.2 to 5.5 V LCD controller/driver
*
Package 80-pin plastic QFP (14 x 14 mm, 0.65-mm pitch) 80-pin plastic TQFP (fine pitch) (12 x 12 mm, 0.5-mm pitch) PROM ( 8 bits) 32768 32768
ORDERING INFORMATION
Part Number
PD75P3018GC-3B9 PD75P3018GK-BE9
Caution
Mask-option pull-up resistors are not provided in this device.
The information in this document is subject to change without notice.
Document No. U10956EJ1V0DS00 (1st edition) (Previous No. IP-3538) Date Published August 1996 P Printed in Japan
The mark
* shows major revised points.
(c)
1994
PD75P3018
FUNCTION OUTLINE
Item Instruction execution time Function * 0.95, 1.91, 3.81, 15.3 s (main system clock: at 4.19 MHz operation) * 0.67, 1.33, 2.67, 10.7 s (main system clock: at 6.0 MHz operation) * 122 s (subsystem clock: at 32.768 kHz operation) 32768 x 8 bits 1024 x 4 bits * 4 bit-operation: 8 4 banks * 8 bit-operation: 4 4 banks 8 16 8 8 40 * Segment number selection : 24/28/32 segments (can be changed to CMOS output port in 4 time-unit; max. 8) * Display mode selection : Static 1/2 duty (1/2 bias) 1/3 duty (1/2 bias) 1/3 duty (1/3 bias) 1/4 duty (1/3 bias) 5 channels: * 8-bit timer/event counter: 3 channels (can be used for 16-bit timer/event counter) * Basic interval timer/watchdog timer: 1 channel * Watch timer: 1 channel * 3-wire serial I/O mode ... MSB or LSB can be selected for transferring top bit * 2-wire serial I/O mode * SBI mode 16 bits * F, 524, 262, 65.5 kHz (main system clock: at 4.19 MHz operation) * F, 750, 375, 93.8 kHz (main system clock: at 6.0 MHz operation) (main system clock: at 4.19 MHz operation or subsystem clock: at 32.768 kHz operation) * 2.86, 5.72, 45.8 kHz (main system clock: at 6.0 MHz operation) * External : 3 * Internal : 5 * External : 1 * Internal : 1 * Ceramic or crystal oscillator for main system clock oscillation * Crystal oscillator for subsystem clock oscillation STOP/HALT mode VDD = 2.2 to 5.5 V * 80-pin plastic QFP (14 x 14 mm) * 80-pin plastic TQFP (fine pitch) (12 x 12 mm) * 2, 4, 32 kHz Also used for segment pins 13-V breakdown voltage On-chip pull-up resistor connection can be specified by using software: 23
Internal memory
PROM RAM
General-purpose register Input/output port CMOS input CMOS input/output CMOS output
*
N-ch open drain input/output Total LCD controller/driver
Timer
Serial interface
Bit sequential buffer (BSB) Clock output (PCL) Buzzer output (BUZ)
Vectored interrupts Test input System clock oscillator Standby function
*
Power supply voltage Package
2
PD75P3018
CONTENTS
1. PIN CONFIGURATION (Top View) .................................................................................................. 2. BLOCK DIAGRAM ........................................................................................................................... 3. PIN FUNCTIONS ..............................................................................................................................
3.1 3.2 3.3 3.4 Port Pins .................................................................................................................................................... Non-port Pins ............................................................................................................................................
4 5 6
6 8
Pin Input/Output Circuits .......................................................................................................................... 10 Recommended Connection for Unused Pins ......................................................................................... 12
4. SWITCHING FUNCTION BETWEEN Mk I AND Mk II MODE .......................................................... 13
4.1 4.2 Difference between Mk I Mode and Mk II Mode ...................................................................................... 13 Setting of Stack Bank Selection Register (SBS) .................................................................................... 14
5. DIFFERENCES BETWEEN PD75P3018 AND PD753012, 753016, AND 753017....................... 15 6. MEMORY CONFIGURATION ........................................................................................................... 16 7. INSTRUCTION SET .......................................................................................................................... 20 8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY ................................................... 30
8.1 8.2 8.3 8.4 Operation Modes for Program Memory Write/Verify ............................................................................. 30 Program Memory Write Procedure .......................................................................................................... 31 Program Memory Read Procedure .......................................................................................................... 32 One-time PROM Screening ...................................................................................................................... 33
9. ELECTRICAL CHARACTERISTICS ................................................................................................ 34 10. PACKAGE DRAWINGS ................................................................................................................... 48 11. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 50 APPENDIX A PD75316B, 753017 AND 75P3018 FUNCTION LIST ................................................... 51 APPENDIX B DEVELOPMENT TOOLS ................................................................................................ 53 APPENDIX C RELATED DOCUMENTS ................................................................................................ 57
* *
*
3
PD75P3018
1. PIN CONFIGURATION (Top View)
* 80-pin plastic QFP (14 14 mm)
PD75P3018GC-3B9
* 80-pin plastic TQFP (fine pitch) (12 12 mm)
PD75P3018GK-BE9
S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24/BP0 S25/BP1 S26/BP2 S27/BP3 S28/BP4 S29/BP5 S30/BP6 S31/BP7
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 60 2 59 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43
S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 RESET P73/KR7 P72/KR6 P71/KR5 P70/KR4 P63/KR3 P62/KR2 P61/KR1
42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P60/KR0 X2 X1 VPP XT2 XT1 VDD P33/MD3 P32/MD2 P31/SYNC/MD1 P30/LCDCL/MD0 P23/BUZ P22/PCL/PTO2 P21/PTO1 P20/PTO0 P13/TI0 P12/INT2/TI1/TI2 P11/INT1 P10/INT0 P03/SI/SB1
PIN IDENTIFICATIONS
P00-P03 P10-P13 P20-P23 P30-P33 P40-P43 P50-P53 P60-P63 P70-P73 BP0-BP7 KR0-KR7 SCK SI SO SB0, 1 RESET MD0-MD3 D0-D7 : Port0 : Port1 : Port2 : Port3 : Port4 : Port5 : Port6 : Port7 : Bit Port 0-7 : Key Return 0-7 : Serial Clock : Serial Input : Serial Output : Serial Bus 0,1 : Reset : Mode Selection 0-3 : Data Bus 0-7 S0-31 COM0-3 VLC0-2 BIAS LCDCL SYNC TI0-2 PTO0-2 BUZ PCL INT0, 1, 4 INT2 X1, 2 XT1, 2 VPP VDD Vss : Segment Output 0-31 : Common Output 0-3 : LCD Power Supply 0-2 : LCD Power Supply Bias Control : LCD Clock : LCD Synchronization : Timer Input 0-2 : Programmable Timer Output 0-2 : Buzzer Clock : Programmable Clock : External Vectored Interrupt 0, 1, 4 : External Test Input 2 : Main System Clock Oscillation 1, 2 : Subsystem Clock Oscillation 1, 2 : Programming Power Supply : Positive Power Supply : Ground
4
COM0 COM1 COM2 COM3 BIAS VLC0 VLC1 VLC2 P40/D0 P41/D1 P42/D2 P43/D3 Vss P50/D4 P51/D5 P52/D6 P53/D7 P00/INT4 P01/SCK P02/SO/SB0
PD75P3018
2. BLOCK DIAGRAM
PTO1/P21
TIMER/EVENT COUNTER #1 INT1 TIMER/EVENT COUNTER #2 INT2 TOUT0 PROGRAM COUNTER (15) ALU SP (8) CY SBS
PORT0
4
P00 to P03
TI1/TI2/ P12/INT2
PORT1
4
P10 to P13
PTO2/P22/PCL
PORT2
4
P20 to P23
BANK PORT3 4
P30 to P33 /MD0 to MD3 P40/D0 to P43/D3 P50/D4 to P53/D7
BASIC INTERVAL TIMER/ WATCHDOG TIMER INTBT TI0/P13 PTO0/P20 TIMER/EVENT COUNTER #0 INT 0 BUZ/P23 WATCH TIMER INTW fLCD SI/SB1/P03 SO/SB0/P02 SCK/P01 CLOCKED SERIAL INTERFACE INTCSI TOUT0 INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0/P60 to KR7/P73 8 fx/2 N BIT SEQ. BUFFER (16) TOUT0
PORT4 GENERAL REG. PROM PROGRAM MEMORY 32768 x 8 BITS
4
PORT5
4
DECODE AND CONTROL
PORT6 RAM DATA MEMORY 1024 x 4 BITS
4
P60 to P63
PORT7
4
P70 to P73
24
S0 to S23 S24/BP0 to S31/BP7 COM0 to COM3 VLC0 to VLC2 BIAS LCDCL/P30 SYNC/P31
8
LCD CONTROLLER /DRIVER
4
INTERRUPT CONTROL fLCD CPU CLOCK
3
SYSTEM CLOCK CLOCK CLOCK GENERATOR STAND BY OUTPUT DIVIDER CONTROL CONTROL SUB MAIN
PCL/P22
XT1 XT2 X1 X2
VDD
VSS RESET VPP
5
PD75P3018
3. PIN FUNCTIONS
3.1 Port Pins (1/2)
Pin name P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 P31 P32 P33 I/O I/O I/O Input I/O I/O I/O Input Shared by INT4 SCK SO/SB0 SI/SB1 INT0 INT1 TI1/TI2/INT2 TI0 PTO0 PTO1 PCL/PTO2 BUZ LCDCL/MD0 SYNC/MD1 MD2 MD3 I/O D0 D1 D2 D3 I/O D4 D5 D6 D7 This is an N-ch open-drain 4-bit I/O port (PORT5). When set to open-drain, voltage is 13 V. Also functions as data I/O pin (upper 4 bits) for program memory (PROM) write/verify. High impedance M-E This is an N-ch open-drain 4-bit I/O port (PORT4). When set to open-drain, voltage is 13 V. Also functions as data I/O pin (lower 4 bits) for program memory (PROM) write/verify. High impedance M-E This is a programmable 4-bit I/O port (PORT3). Input and output in single-bit units can be specified. When set for 4-bit units, an internal pull-up resistor connection can be specified by software. -- Input E-B This is a 4-bit I/O port (PORT2). These are 4-bit pins for which an internal pull-up resistor connection can be specified by software. -- Input E-B This is a 4-bit input port (PORT1). These are 4-bit pins for which an internal pull-up resistor connection can be specified by software. INT0 includes noise elimination function. -- Input Function This is a 4-bit input port (PORT0). P01 to P03 are 3-bit pins for which an internal pull-up resistor connection can be specified by software. 8-bit I/O -- Status after reset Input I/O circuit type Note 1 -A -B -C -C
* *
P40 Note 2 P41 Note 2 P42 Note 2 P43 Note 2 P50 Note 2 P51 Note 2 P52 Note 2 P53 Note 2
Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input. 2. Low-level input leakage current increases when input instructions or bit manipulation instructions are executed.
6
PD75P3018
3.1 Port Pins (2/2)
Pin name P60 P61 P62 P63 P70 P71 P72 P73 BP0 BP1 BP2 BP3 BP4 BP5 BP6 BP7 I/O I/O I/O Shared by KR0 KR1 KR2 KR3 KR4 KR5 KR6 KR7 Output S24 S25 S26 S27 Output S28 S29 S30 S31 1-bit I/O port (BIT PORT). These pins are also used as segment output pin. -- Note 2 H-A This is a 4-bit I/O port (PORT7). When set for 4-bit units, an internal pull-up resistor connection can be specified by software. Input -A Function This is a programmable 4-bit I/O port (PORT6). Input and output in single-bit units can be specified. When set for 4-bit units, an internal pull-up resistor connection can be specified by software. 8-bit I/O Status after reset Input I/O circuit type Note 1 -A
Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input. 2. VLC1 is selected as the input source for BP0 to BP7. The output level varies depending on the external circuit for BP0 to BP7 and VLC1. Example: As shown below, BP0 to BP7 are mutually connected via the PD75P3018, so the output levels of BP0 to BP7 are determined by the sizes of R1, R2, and R3.
VDD
R2 BP0 ON VLC1
BP1 R1 ON R3 PD75P3018
7
PD75P3018
3.2 Non-port Pins (1/2)
Pin name TI0 TI1, TI2 PTO0 PTO1 PTO2 PCL BUZ SCK SO/SB0 SI/SB1 INT4 INT0 INT1 INT2 KR0-KR3 KR4-KR7 X1 X2 XT1 XT2 RESET MD0 MD1 MD2, MD3 D0-D3 D4-D7 VPP -- I/O Input I/O I/O Input -- Input -- Input I/O -- P30/LCDCL P31/SYNC P32, P33 P40-P43 P50-P53 -- Programmable power supply voltage for program memory (PROM) write/verify. For normal operation, connect directly to VDD. Apply +12.5 V for PROM write/verify. Positive power supply Ground -- -- Data bus for program memory (PROM) write/verify Input M-E -- I/O Input Input I/O Shared by P13 P12/INT2 P20 P21 P22 Output P22 I/O I/O I/O I/O Input Input P23 P01 P02 P03 P00 P10 P11 P12/TI1/TI2 P60-P63 P70-P73 -- Rising edge detection test input Parallel falling edge detection test input Parallel falling edge detection test input Ceramic/crystal oscillation circuit connection for main system clock. If using an external clock, input to X1 and input inverted phase to X2. Crystal oscillation circuit connection for subsystem clock. If using an external clock, input to XT1 and input inverted phase to XT2. XT1 can be used as a 1-bit (test) input. System reset input Mode selection for program memory (PROM) write/verify Clock output Frequency output (for buzzer or system clock trimming) Serial clock I/O Serial data output Serial data bus I/O Serial data input Serial data bus I/O Edge detection vectored interrupt input (valid for detecting both rising and falling edges) Edge detection vectored interrupt input Clock synch/asynch (detected edge is selectable) is selectable Asynch Asynch Input Input Input -- -C -A -A -- Input Input Input Input Input Input Input E-B E-B -A -B -C -C Timer/event counter output Input E-B Function External event pulse input to timer/event counter Status after reset Input I/O circuit typeNote -C
--
--
-- Input
E-B
VDD Vss
-- --
-- --
-- --
-- --
Note Circuit types enclosed in brackets indicate Schmitt trigger input.
8
PD75P3018
3.2 Non-port Pins (2/2)
Pin name S0-S23 S24-S31 I/O Output Shared by -- Segment signal output Segment signal output Common signal output Power source for LCD driver Output for external split resistor cut Clock output for driving external expansion driver Clock output for synchronization of external expansion driver Function Status after reset Note 1 Note 1 Note 1 -- High impedance Input Input I/O circuit type G-A H-A G-B -- -- E-B E-B
Output BP0-BP7 -- -- -- P30 P31
COM0-COM3 Output VLC0-VLC2 BIAS LCDCLNote 2 SYNC
Note 2
-- Output I/O I/O
Notes 1. The VLCX (X = 0, 1, 2) shown below are selected as the input source for the display outputs. S0-S31: VLC1, COM0-COM2: VLC2, COM3: VLC0 2. These pins are provided for future system expansion. Currently, only P30 and P31 are used.
9
PD75P3018
3.3 Pin Input/Output Circuits The input/output circuits for the PD75P3018's pins are shown in abbreviated form below.
TYPE A VDD Data P-ch IN Output disable N-ch TYPE D VDD P-ch OUT
N-ch
CMOS standard input buffer
Push-pull output that can be set to high impedance output (with both P-ch and N-ch OFF). TYPE E-B VDD P.U.R. P.U.R. enable P-ch
TYPE B
IN Data Type D Output disable IN/OUT
Type A Schmitt trigger input with hysteresis characteristics. P.U.R. : Pull-Up Resistor
TYPE B-C
TYPE F-A VDD VDD P.U.R. P.U.R. enable P.U.R. enable Data Type D Output disable IN Type B P.U.R. : Pull-Up Resistor P.U.R. : Pull-Up Resistor P.U.R. P-ch
P-ch
IN/OUT
(Continued)
10
PD75P3018
TYPE F-B VDD P.U.R. P.U.R. enable Output disable (P) Data Output disable Output disable (N) N-ch VDD P-ch IN/OUT P-ch
TYPE H-A
*
IN/OUT
SEG data
Type G-A
Bit Port data Output disable
Type E-B
P.U.R. : Pull-Up Resistor TYPE G-A
*
VLC0 VLC1 P-ch N-ch P-ch
TYPE M-C VDD P.U.R. P.U.R. enable P-ch IN/OUT OUT Data Output disable N-ch
SEG data VLC2 N-ch
N-ch
P.U.R. : Pull-Up Resistor
TYPE G-B
TYPE M-E
*
IN/OUT VDD N-ch (+13-V breakdown voltage)
VLC0 VLC1
Data P-ch Output disable P-ch N-ch
Input instruction
P-ch P.U.R.
Note
OUT COM data N-ch P-ch VLC2 N-ch
Voltage controller
(+13-V breakdown voltage)
Note Pull-up resistor operated only when executing input instructions (when pins are low level, current flows from VDD to pins).
11
PD75P3018
3.4 Recommended Connection for Unused Pins
Pin P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0, P11/INT1 P12/TI1/TI2/INT2 P13/TI0 P20/PTO0 P21/PTO1 P22/PTO2/PCL P23/BUZ P30/LCDCL/MD0 P31/SYNC/MD1 P32/MD2, P33/MD3 P40-P43 P50-P53 P60/KR0-P63/KR3 P70/KR4-P73/KR7 S0-S23 S24/BP0-S31/BP7 COM0-COM3 VLC0-VLC2 BIAS XT1 Note XT2
Note
Recommended connection Connect to VSS or VDD Connect to VSS or VDD
Connect to VSS Connect to VSS or VDD
Input status
:connect to Vss or VDD through individual resistor
Output status :open
Open
Connect to Vss Connect to Vss only when VLC0 to VLC2 are all not used. In other cases, leave open. Connect to Vss Open
*
Note When subsystem clock is not used, specify SOS.0 = 1 (indicates that internal feedback resistor is disconnected).
12
PD75P3018
4. SWITCHING FUNCTION BETWEEN Mk I AND Mk II MODE
Setting a stack bank selection (SBS) register for the PD75P3018 enables the program memory to be switched between Mk I mode and Mk II mode. This function is applicable when using the PD75P3018 to evaluate the PD753012, 753016, or 753017. When the SBS bit 3 is set to 1 : sets Mk I mode (supports Mk I mode for PD753012, 753016, and 753017) When the SBS bit 3 is set to 0 : sets Mk II mode (supports Mk II mode for PD753012, 753016, and 753017) 4.1 Difference between Mk I Mode and Mk II Mode Table 4-1 lists points of difference between the Mk I mode and the Mk II mode for the PD75P3018. Table 4-1. Difference between Mk I Mode and Mk II Mode
Item Program counter Program memory (bytes) Data memory (bits) Stack Stack bank No. of stack bytes Instruction BRA !addr1 instruction CALLA !addr1 instruction Instruction CALL !addr instruction 3 machine cycles 2 machine cycles When set to Mk I mode: PD753012, 753016, and 753017 4 machine cycles 3 machine cycles When set to Mk II mode: PD753012, 753016, and 753017 Mk I Mode PC13-0 PC14 is fixed at 0 16384 1024 x 4 Selectable via memory banks 0 to 3 2 bytes Use disabled 3 bytes Use enabled PC14-0 32768 Mk II Mode
execution time CALLF !faddr instruction Supported mask ROMs
Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL series. Therefore, this mode is effective for enhancing software compatibility with products that have a program area of more than 16 Kbytes. With regard to the number of stack bytes during execution of subroutine call instructions, the usable area increases by 1 byte per stack compared to the Mk I mode when the Mk II mode is selected. However, when the CALL !addr and CALLF !faddr instructions are used, the machine cycle becomes longer by 1 machine cycle. Therefore, if more emphasis is placed on RAM use efficiency and processing performance than on software compatibility, the Mk I mode should be used.
*
13
PD75P3018
4.2 Setting of Stack Bank Selection Register (SBS) Use the stack bank selection register to switch between Mk I mode and Mk II mode. Figure 4-1 shows the format for doing this. The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be sure to initialize the stack bank selection register to 10XXBNote at the beginning of the program. When using the Mk II mode, be sure to initialize it to 00XXBNote. Note Set the desired value for XX. Figure 4-1. Format of Stack Bank Selection Register
Address F84H
3 SBS3
2 SBS2
1 SBS1
0 SBS0
Symbol SBS
Stack area specification
0 0 1 1 0 1 0 1 Memory bank 0 Memory bank 1 Memory bank 2 Memory bank 3
0
Be sure to enter "0" for bit 2.
Mode selection specification
0 1 Mk II mode Mk I mode
Cautions 1. SBS3 is set to "1" after RESET input, and consequently the CPU operates in Mk I mode. When using instructions for Mk II mode, set SBS3 to "0" and set Mk II mode before using the instructions. 2. When using Mk II mode, execute a subroutine call instruction and an interrupt instruction after RESET input and after setting the stack bank selection register.
14
PD75P3018
5. DIFFERENCES BETWEEN PD75P3018 AND PD753012, 753016, AND 753017
The PD75P3018 replaces the internal mask ROM in the PD753012, 753016, and 753017 with a one-time PROM and features expanded ROM capacity. The PD75P3018's Mk I mode supports the Mk I mode in the PD753012, 753016, and 753017 and the PD75P3018's Mk II mode supports the Mk II mode in the PD753012, 753016, and 753017. Table 5-1 lists differences among the PD75P3018 and the PD753012, 753016, and 753017. Be sure to check the differences among these products before using them with PROMs for debugging or prototype testing of application systems or, later, when using them with a mask ROM for full-scale production. For the CPU functions and internal hardwares, refer to PD753017 User's Manual (U11282E). Table 5-1. Differences between PD75P3018 and PD753012, 753016, and 753017
Item Program counter Program memory (bytes) During Mk I mode During Mk II mode Data memory (x 4 bits) Mask options Pull-up resistor for PORT4 and PORT5 LCD split resistor Feed back resistor for subsystem clock Wait time during RESET Pin configuration Pin Nos. 29 to 32 Pin Nos. 34 to 37 Pin No. 50 Pin No. 51 Pin Nos. 52 and 53 Pin No. 57 Other Yes (Can be specified with the SOS register whether to incorporate or not) Yes (Can be specified either 2 /fX or 2 /fX) P40 to P43 P50 to P53 P30/LCDCL P31/SYNC P32, P33 IC
17 15 Note
PD753012 14 bits Mask ROM 12288 12288 1024
PD753016
PD753017 15 bits
PD75P3018
One-time PROM 16384 16384 16384 24576 16384 32768
Yes (Can be specified whether to incorporate or not)
No (Cannot incorporate)
No (Cannot incorporate) No (Fixed at 2 /fX)
15 Note
* *
P40/D0 to P43/D3 P50/D4 to P53/D7 P30/LCDCL/MD0 P31/SYNC/MD1 P32/MD2, P33/MD3 VPP
Noise resistance and noise radiation may differ due to the different circuit sizes and mask layouts.
Note For 217/fX, during 6.0 MHz operation is 21.8 ms, and during 4.19 operation is 31.3 ms. For 215/fX, during 6.0 MHz operation is 5.46 ms, and during 4.19 operation is 7.81 ms. Caution Noise resistance and noise radiation are different in PROM and mask ROMs. In transferring to mask ROM versions from the PROM version in a processe between prototype development and full production, be sure to fully evaluate the mask ROM version's CS (not ES).
15
PD75P3018
6. MEMORY CONFIGURATION
6.1 Program Counter (PC) ... 15 bits This is a 15-bit binary counter that stores program memory address data. Bit 15 is valid during Mk II mode. But PC14 is fixed at zero during Mk I mode, and the lower 14 bits are all valid. Figure 6-1. Configuration of Program Counter
PC14
PC13
PC12
PC11
PC10
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PC
Fixed at zero during Mk I mode
6.2 Program Memory (PROM) ... 32768 x 8 bits The program memory consists of 32768 x 8-bit one-time PROM. The program memory address can be selected as shown below by setting the stack bank selection (SBS) register.
Mk I mode Usable address 0000H to 3FFFH Mk II mode 0000H to 7FFFH
Figures 6-2 and 6-3 show the addressing ranges for the program memory and branch instruction and the subroutine call instruction, during Mk I and Mk II modes.
16
PD75P3018
Figure 6-2. Program Memory Map (Mk I mode)
7 0000H MBE 6 RBE 5 0
Internal reset start address (upper 6 bits) Internal reset start address (lower 8 bits)
0002H
MBE
RBE
INTBT/INT4 start address (upper 6 bits) INTBT/INT4 start address (lower 8 bits) CALLF !faddr instruction entry address
0004H
MBE
RBE
INT0 start address (upper 6 bits) INT0 start address (lower 8 bits)
0006H
MBE
RBE
INT1 start address (upper 6 bits) INT1 start address (lower 8 bits) BRCB !caddr instruction branch address
0008H
MBE
RBE
INTCSI start address (upper 6 bits) INTCSI start address (lower 8 bits)
000AH
MBE
RBE
INTT0 start address (upper 6 bits) INTT0 start address (lower 8 bits) * BR BCDE instruction * BR BCXA instruction * BR !addr instruction * CALL !addr instruction branch address Branch/call address by GETI
000CH
MBE
RBE
INTT1, INTT2 start address (upper 6 bits) INTT1, INTT2 start address (lower 8 bits)
0020H Reference table for GETI instruction 007FH 0080H 07FFH 0800H 0FFFH 1000H 1FFFH 2000H 2FFFH 3000H 3FFFH
BR $addr instruction relative branch address (-15 to -1, +2 to +16)
BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address
Remark
For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to branch to addresses with changes in the PC's lower 8 bits only.
17
PD75P3018
Figure 6-3. Program Memory Map (Mk II mode)
7 0000H MBE 6 RBE 5 0 Internal reset start address (upper 6 bits) Internal reset start address (lower 8 bits) 0002H MBE RBE INTBT/INT4 start address (upper 6 bits) INTBT/INT4 start address (lower 8 bits) 0004H MBE RBE INT0 start address (upper 6 bits) INT0 start address (lower 8 bits) 0006H MBE RBE INT1 start address (upper 6 bits) INT1 start address (lower 8 bits) 0008H MBE RBE INTCSI start address (upper 6 bits) INTCSI start address (lower 8 bits) 000AH MBE RBE INTT0 start address (upper 6 bits) INTT0 start address (lower 8 bits) 000CH MBE RBE INTT1, INTT2 start address (upper 6 bits) INTT1, INTT2 start address (lower 8 bits) BRCB !caddr instruction branch address CALLF !faddr instruction entry address
Branch addresses for the following instructions * BR BCDE * BR BCXA * BRA !addr1 * CALLA !addr1
BR $addr1 instruction relative branch address (-15 to -1, +2 to +16)
0020H Reference table for GETI instruction 007FH 0080H 07FFH 0800H 0FFFH 1000H 1FFFH 2000H 2FFFH 3000H 3FFFH 4000H 4FFFH 5000H 5FFFH 6000H 6FFFH 7000H 7FFFH
BR !addr instruction branch address CALL !addr instruction branch address Branch/call address by GETI BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address
Caution To allow the vectored interrupt's 14-bit start address (noted above), set the address within a 16-K area (0000H to 3FFFH). Remark For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to branch to addresses with changes in the PC's lower 8 bits only.
18
PD75P3018
6.3 Data Memory (RAM) ... 1024 x 4 bits Figure 6-4 shows the data memory configuration. Data memory consists of a data area and a peripheral hardware area. The data area consists of 1024 x 4-bit static RAM. Figure 6-4. Data Memory Map
Data memory 000H General-purpose register area 01FH 020H 0 256 x 4 (248 x 4) 0FFH 100H 256 x 4 (224 x 4) 1DFH 1E0H Display data memory 1FFH 200H Data area static RAM (1024 x 4) Stack area Note 256 x 4 2 (32 x 4) 1 (8 x 4) Memory bank
2FFH 300H
256 x 4
3
3FFH
Not incorporated
F80H
Peripheral hardware area
128 x 4
15
FFFH
Note Memory bank 0, 1, 2, or 3 can be selected as the stack area.
19
PD75P3018
7. INSTRUCTION SET
(1) Representation and coding formats for operands In the instruction's operand area, use the following coding format to describe operands corresponding to the instruction's operand representations (for further description, see theRA75X Assembler Package User's Manual -Language (EEU1363)). When there are several codes, select and use just one. Codes that consist of upper-case letters and + or - symbols are key words that should be entered as they are. For immediate data, enter an appropriate numerical value or label. Enter register flag symbols as label descriptors instead of mem, fmem, pmem, bit, etc. (For details, refer to the User's Manual). The number of labels that can be entered for fmem and pmem are restricted.
Representation reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr addr1 caddr faddr taddr PORTn IEXXX RBn MBn X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA', BC', DE', HL' BC, DE, HL, XA', BC', DE', HL' HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or labelNote 2-bit immediate data or label FB0H-FBFH, FF0H-FFFH immediate data or label FC0H-FFFH immediate data or label 0000H-3FFFH immediate data or label (Mk I mode and Mk II mode) 0000H-7FFFH immediate data or label (Mk II mode only) 12-bit immediate data or label 11-bit immediate data or label 20H-7FH immediate data (however, bit0 = 0) or label PORT0-PORT7 IEBT, IECSI, IET0, IET1, IET2, IE0-IE2, IE4, IEW RB0-RB3 MB0-MB3, MB15 Coding format
Note When processing 8-bit data, only even-numbered addresses can be specified.
20
PD75P3018
(2) Operation legend A B C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP CY PSW MBE RBE IME IPS IEXXX RBS MBS PCC . (XX) XXH : A register; 4-bit accumulator : B register : C register : D register : E register : H register : L register : X register : Register pair (XA); 8-bit accumulator : Register pair (BC) : Register pair (DE) : Register pair (HL) : Expansion register pair (XA') : Expansion register pair (BC') : Expansion register pair (DE') : Expansion register pair (HL') : Program counter : Stack pointer : Carry flag; bit accumulator : Program status word : Memory bank enable flag : Register bank enable flag : Interrupt master enable flag : Interrupt priority selection register : Interrupt enable flag : Register bank selection register : Memory bank selection register : Processor clock control register : Delimiter for address and bit : Addressed data : Hexadecimal data
PORTn : Port n (n = 0 to 7)
21
PD75P3018
(3) Description of symbols used in addressing area
MB = MBE * MBS *1 MBS = 0-3, 15 *2 *3 MB = 0 MBE = 0 : MB = 0 (000H-07FH) MB = 15 (F80H-FFFH) MBE = 1 : MB = MBS MBS = 0-3, 15 *4 *5 *6 *7 MB = 15, fmem = FB0H-FBFH, FF0H-FFFH MB = 15, pmem = FC0H-FFFH addr = 0000H-3FFFH addr, addr1 = (Current PC) -15 to (Current PC) -1 (Current PC) +2 to (Current PC) +16 *8 caddr = 0000H-0FFFH (PC14, 13, 12 = 000B: Mk I or Mk II mode) or 1000H-1FFFH (PC14, 13, 12 = 001B: Mk I or Mk II mode) or 2000H-2FFFH (PC14, 13, 12 = 010B: Mk I or Mk II mode) or 3000H-3FFFH (PC14, 13, 12 = 011B: Mk I or Mk II mode) or 4000H-4FFFH (PC14, 13, 12 = 100B: Mk II mode) or 5000H-5FFFH (PC14, 13, 12 = 101B: Mk II mode) or 6000H-6FFFH (PC14, 13, 12 = 110B: Mk II mode) or 7000H-7F7FH (PC14, 13, 12 = 111B: Mk II mode) *9 *10 *11 faddr = 0000H-07FFH taddr = 0020H-007FH addr1 = 0000H-7FFFH (Mk II mode only) Program memory addressing Data memory addressing
Remarks 1. MB indicates access-enabled memory banks. 2. In area *2, MB = 0 for both MBE and MBS. 3. In areas *4 and *5, MB = 15 for both MBE and MBS. 4. Areas *6 to *11 indicate corresponding address-enabled areas.
22
PD75P3018
(4) Description of machine cycles S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies as shown below. * No skip ..................................................................... S = 0 * Skipped instruction is 1-byte or 2-byte instruction .... S = 1 * Skipped instruction is 3-byte instructionNote .............. S = 2 Note 3-byte instructions: BR !addr, BRA !addr1, CALL !addr, CALLA !addr1 Caution The GETI instruction is skipped for one machine cycle. One machine cycle equals one cycle (= tCY) of the CPU clock F. Use the PCC setting to select among four cycle times.
23
PD75P3018
Instruction group Transfer
Mnemonic MOV
Operand A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL @HL, A @HL, XA A, mem XA, mem mem, A mem, XA A, reg1 XA, rp' reg1, A rp'1, XA
No. of Machine bytes cycle 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1 1 1 1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 3 3 3 3 A<-n4 reg1<-n4 XA<-n8 HL<-n8 rp2<-n8 A<-(HL)
Operation
Addressing area
Skip condition String-effect A
String-effect A String-effect B
*1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L=FH
A<-(HL), then L<-L+1 A<-(HL), then L<-L-1 A<-(rpa1) XA<-(HL) (HL)<-A (HL)<-XA A<-(mem) XA<-(mem) (mem)<-A (mem)<-XA A<-reg1 XA<-rp' reg1<-A rp'1<-XA A<->(HL) A<->(HL), then L<-L+1 A<->(HL), then L<-L-1 A<->(rpa1) XA<->(HL) A<->(mem) XA<->(mem) A<->reg1 XA<->rp' XA<-(PC13-8+DE)ROM XA<-(PC13-8+XA)ROM XA<-(BCDE)ROM Note XA<-(BCXA)ROM
Note
XCH
A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL A, mem XA, mem A, reg1 XA, rp'
*1 *1 *1 *2 *1 *3 *3 L=0 L=FH
Table reference
MOVT
XA, @PCDE XA, @PCXA XA, @BCDE XA, @BCXA
*11 *11
Note Only the lower 3 bits in the B register are valid.
24
PD75P3018
Instruction group Bit transfer
Mnemonic MOV1
Operand CY, fmem.bit CY, pmem.@L CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY
No. of Machine bytes cycle 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1 1 2 2 1 2 2 2 2 2 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1+S 1+S 2+S 2+S 1+S 2+S
Operation CY<-(fmem.bit) CY<-(pmem7-2+L3-2.bit(L1-0)) CY<-(H+mem3-0.bit) (fmem.bit)<-CY (pmem7-2+L3-2.bit(L1-0))<-CY (H+mem3-0.bit)<-CY A<-A+n4 XA<-XA+n8 A<-A+(HL) XA<-XA+rp' rp'1<-rp'1+XA A, CY<-A+(HL)+CY XA, CY<-XA+rp'+CY rp'1, CY<-rp'1+XA+CY A<-A-(HL) XA<-XA-rp' rp'1<-rp'1-XA A, CY<-A-(HL)-CY XA, CY<-XA-rp'-CY rp'1, CY<-rp'1-XA-CY A<-A^n4 A<-A^(HL) XA<-XA^rp' rp'1<-rp'1^XA A<-Avn4 A<-Av(HL) XA<-XAvrp' rp'1<-rp'1vXA A<-Avn4 A<-Av(HL) XA<-XAvrp' rp'1<-rp'1vXA CY<-A0, A3<-CY, An-1<-An A<-A reg<-reg+1 rp1<-rp1+1 (HL)<-(HL)+1 (mem)<-(mem)+1 reg<-reg-1 rp'<-rp'-1
Addressing area *4 *5 *1 *4 *5 *1
Skip condition
Arithmetic
ADDS
A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA
carry carry *1 carry carry carry *1
ADDC
A, @HL XA, rp' rp'1, XA
SUBS
A, @HL XA, rp' rp'1, XA
*1
borrow borrow borrow
SUBC
A, @HL XA, rp' rp'1, XA
*1
AND
A, #n4 A, @HL XA, rp' rp'1, XA
*1
OR
A, #n4 A, @HL XA, rp' rp'1, XA
*1
XOR
A, #n4 A, @HL XA, rp' rp'1, XA
*1
Accumulator manipulation Increment/ decrement
RORC NOT INCS
A A reg rp1 @HL mem
reg=0 rp1=00H *1 *3 (HL)=0 (mem)=0 reg=FH rp'=FFH
DECS
reg rp'
25
PD75P3018
Instruction group Comparison
Mnemonic SKE
Operand reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp'
No. of Machine bytes cycle 2 2 1 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2 Skip if reg=n4
Operation
Addressing area
Skip condition reg=n4
Skip if (HL)=n4 Skip if A=(HL) Skip if XA=(HL) Skip if A=reg Skip if XA=rp' CY<-1 CY<-0 Skip if CY=1 CY<-CY (mem.bit)<-1 (fmem.bit)<-1 (pmem7-2+L3-2.bit(L1-0))<-1 (H+mem3-0.bit)<-1 (mem.bit)<-0 (fmem.bit)<-0 (pmem7-2+L3-2.bit(L1-0))<-0 (H+mem3-0.bit)<-0 Skip if(mem.bit)=1 Skip if(fmem.bit)=1 Skip if(pmem7-2+L3-2.bit(L1-0))=1 Skip if(H+mem3-0.bit)=1 Skip if(mem.bit)=0 Skip if(fmem.bit)=0 Skip if(pmem7-2+L3-2.bit(L1-0))=0 Skip if(H+mem3-0.bit)=0 Skip if(fmem.bit)=1 and clear Skip if(pmem7-2+L3-2.bit (L1-0))=1 and clear Skip if(H+mem3-0.bit)=1 and clear CY<-CY^(fmem.bit) CY<-CY^(pmem7-2+L3-2.bit(L1-0)) CY<-CY^(H+mem3-0.bit) CY<-CYv(fmem.bit) CY<-CYv(pmem7-2+L3-2.bit(L1-0)) CY<-CYv(H+mem3-0.bit) CY<-CYv (fmem.bit) CY<-CYv(pmem7-2+L3-2.bit(L1-0)) CY<-CYv(H+mem3-0.bit)
*1 *1 *1
(HL)=n4 A=(HL) XA=(HL) A=reg XA=rp'
Carry flag manipulation
SET1 CLR1 SKT NOT1
CY CY CY CY mem.bit fmem.bit pmem.@L @H+mem.bit
CY=1
Memory bit manipulation
SET1
*3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 (mem.bit)=1 (fmem.bit)=1 (pmem.@L)=1 (@H+mem.bit)=1 (mem.bit)=0 (fmem.bit)=0 (pmem.@L)=0 (@H+mem.bit)=0 (fmem.bit)=1 (pmem.@L)=1 (@H+mem.bit)=1
CLR1
mem.bit fmem.bit pmem.@L @H+mem.bit
SKT
mem.bit fmem.bit pmem.@L @H+mem.bit
SKF
mem.bit fmem.bit pmem.@L @H+mem.bit
SKTCLR
fmem.bit pmem.@L @H+mem.bit
AND1
CY, fmem.bit CY, pmem.@L CY, @H+mem.bit
OR1
CY, fmem.bit CY, pmem.@L CY, @H+mem.bit
XOR1
CY, fmem.bit CY, pmem.@L CY, @H+mem.bit
26
PD75P3018
Instruction group Branch
Mnemonic BR Note 1
Operand addr
No. of Machine bytes cycle -- --
Operation PC14<-0, PC13-0<-addr Use the assembler to select the most appropriate instruction among the following. * BR !addr * BRCB !caddr * BR $addr PC14-0<-addr1 Use the assembler to select the most appropriate instruction among the following. * BRA !addr1 * BR !addr * BRCB !caddr * BR $addr1 PC14<-0, PC13-0<-addr PC14<-0, PC13-0<-addr PC14<-0, PC13-0<-addr1 PC14-0<-addr1
Addressing area *6
Skip condition
addr1
--
--
*11
!addr $addr $addr1
3 1 1
3 2 2
*6 *7
PCDE
2
3
PC14<-0, PC13-0<-PC13-8+DE PC14-0<-PC14-8+DE
PCXA
2
3
PC14<-0, PC13-0<-PC13-8+XA PC14-0<-PC14-8+XA
BCDE
2
3
PC14<-0, PC13-0<-BCDE Note 2 PC14-0<-BCDE
Note 2
*11
BCXA
2
3
PC14<-0, PC13-0<-BCXA Note 2 PC14-0<-BCXA
Note 2
*11
BRA
Note 1
!addr1 !caddr
3 2
3 2
PC14-0<-addr1 PC14<-0, PC13-0<-PC13, 12+caddr11-0 PC14-0<-PC14, 13, 12+caddr11-0
*11 *8
BRCB
Notes 1. Shaded areas indicate support for Mk II mode only. 2. The only following bits are valid in the B register. For Mk I mode : Lower 2 bits For Mk II mode : Lower 3 bits
27
PD75P3018
Instruction group Subroutine stack control
Mnemonic CALLA Note
Operand !addr1
No. of Machine bytes cycle 3 3
Operation (SP-5)<-0, PC14-12 (SP-6)(SP-3)(SP-4)<-PC11-0 (SP-2)<-X, X, MBE, RBE PC14-0<-addr1, SP<-SP-6
Addressing area *11
Skip condition
CALL
Note
!addr
3
3
(SP-4)(SP-1)(SP-2)<-PC11-0 (SP-3)<-MBE, RBE, PC13, 12 PC14<-0, PC13-0<-addr, SP<-SP-4
*6
4
(SP-5)<-0, PC14-12 (SP-6)(SP-3)(SP-4)<-PC11-0 (SP-2)<-X, X, MBE, RBE PC14<-0, PC13-0<-addr, SP<-SP-6
CALLF Note
!faddr
2
2
(SP-4)(SP-1)(SP-2)<-PC11-0 (SP-3)<-MBE, RBE, PC13, 12 PC14<-0, PC13-0<-000+faddr, SP<-SP-4
*9
3
(SP-5)<-0, PC14-12 (SP-6)(SP-3)(SP-4)<-PC11-0 (SP-2)<-X, X, MBE, RBE PC14-0<-0000+faddr, SP<-SP-6
RET
Note
1
3
MBE, RBE, PC13, 12<-(SP+1) PC11-0<-(SP)(SP+3)(SP+2) PC14<-0, SP<-SP+4 X, X, MBE, RBE<-(SP+4) 0, PC14-12<-(SP+1) PC11-0<-(SP)(SP+3)(SP+2) SP<-SP+6
RETS Note
1
3+S
MBE, RBE, PC13, 12<-(SP+1) PC11-0<-(SP)(SP+3)(SP+2) PC14<-0, SP<-SP+4 then skip unconditionally X, X, MBE, RBE<-(SP+4) 0, PC14-12<-(SP+1) PC11-0<-(SP)(SP+3)(SP+2) SP<-SP+6 then skip unconditionally
Unconditional
RETI Note
1
3
PC13, 12<-(SP+1)1, 0, PC14<-0 PC11-0<-(SP)(SP+3)(SP+2) PSW<-(SP+4)(SP+5), SP<-SP+6 0, PC14-12<-(SP+1) PC11-0<-(SP)(SP+3)(SP+2) PSW<-(SP+4)(SP+5), SP<-SP+6
Note Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only.
28
PD75P3018
Instruction group Subroutine stack control
Mnemonic PUSH rp BS POP rp BS
Operand
No. of Machine bytes cycle 1 2 1 2 2 1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 2 2 3
Operation (SP-1)(SP-2)<-rp, SP<-SP-2 (SP-1)<-MBS, (SP-2)<-RBS, SP<-SP-2 rp<-(SP+1)(SP), SP<-SP+2 MBS<-(SP+1), RBS<-(SP), SP<-SP+2 IME(IPS.3)<-1 IEXXX<-1 IME(IPS.3)<-0 IEXXX<-0 A<-PORTn (n=0-7)
Addressing area
Skip condition
Interrupt control
EI IEXXX DI IEXXX
2 2 2 2 2 2 2 2 2 1
I/O
IN
Note 1
A, PORTn XA, PORTn
XA<-PORTn+1, PORTn (n=4, 6) PORTn<-A (n=2-7)
OUT Note 1
PORTn, A PORTn, XA
PORTn+1, PORTn<-XA (n=4, 6) Set HALT Mode(PCC.2<-1) Set STOP Mode(PCC.3<-1) No Operation RBS<-n (n=0-3) MBS<-n (n=0-3, 15) * When using TBR instruction PC13-0<-(taddr)5-0+(taddr+1), PC14<-0
--------------------------------------
CPU control
HALT STOP NOP
Special
SEL
RBn MBn
2 2 1
GETI
Note 2, 3
taddr
*10
* When using TCALL instruction (SP-4)(SP-1)(SP-2)<-PC11-0 (SP-3)<-MBE, RBE, PC13, 12, PC14<-0 PC13-0<-(taddr)5-0+(taddr+1) SP<-SP-4
--------------------------------------
* When using instruction other than TBR or TCALL Execute (taddr)(taddr+1) instructions 1 3 * When using TBR instruction PC13-0<-(taddr)5-0+(taddr+1), PC14<-0
--------------------------------
Determined by referenced instruction *10
------------
4
* When using TCALL instruction (SP-5)<-0, PC14-12 (SP-6)(SP-3)(SP-4)<-PC11-0 (SP-2)<-X, X, MBE, RBE, PC14<-0 PC13-0<-(taddr)5-0+(taddr+1) SP<-SP-6
--------------------------------
------------
3
* When using instruction other than TBR or TCALL Execute (taddr)(taddr+1) instructions
Determined by referenced instruction
Notes 1. Before executing the IN or OUT instruction, set MBE to 0 or 1 and set MBS to 15. 2. TBR and TCALL are assembler pseudo-instructions for the GETI instruction's table definitions. 3. Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only.
29
PD75P3018
8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY
The program memory contained in the PD75P3018 is a 32768 x 8-bit one-time PROM that can be electrically written one time only. The pins listed in the table below are used for this PROM's write/verify operations. Clock input from the X1 pin is used instead of address input as a method for updating addresses.
Pin VPP X1, X2 Function Pin where program voltage is applied during program memory write/verify (usually VDD potential) Clock input pins for address updating during program memory write/verify. Input the X1 pin's inverted signal to the X2 pin. Operation mode selection pin for program memory write/verify 8-bit data I/O pins for program memory write/verify
MD0-MD3 D0/P40 to D3/P43 (lower 4 bits) D4/P50 to D7/P53 (upper 4 bits)
*
VDD
Pin where power supply voltage is applied. Applies VDD = 2.2 to 5.5 V in normal operation mode and +6 V for program memory write/verify.
Caution Pins not used for program memory write/verify should be connected to Vss.
8.1 Operation Modes for Program Memory Write/Verify When +6 V is applied to the VDD pin and +12.5 V to the VPP pin, the PD75P3018 enters the program memory write/verify mode. The following operation modes can be specified by setting pins MD0 to MD3 as shown below.
Operation mode specification VPP +12.5 V VDD +6 V MD0 H L L H MD1 L H L X MD2 H H H H MD3 L H H H Zero-clear program memory address Write mode Verify mode Program inhibit mode Operation mode
X: L or H
30
PD75P3018
8.2 Program Memory Write Procedure Program memory can be written at high speed using the following procedure. (1) Pull unused pins to Vss through resistors. Set the X1 pin low. (2) Supply 5 V to the VDD and VPP pins. (3) Wait 10 s. (4) Select the zero-clear program memory address mode. (5) Supply 6 V to the VDD and 12.5 V to the VPP pins. (6) Select the program inhibit mode. (7) Write data in the 1 ms write mode. (8) Select the program inhibit mode. (9) Select the verify mode. If the data is correct, go to step (10) and if not, repeat steps (7) to (9). (10) (X : number of write operations from steps (7) to (9)) x 1 ms additional write. (11) Select the program inhibit mode. (12) Apply four pulses to the X1 pin to increment the program memory address by one. (13) Repeat steps (7) to (12) until the end address is reached. (14) Select the zero-clear program memory address mode. (15) Return the VDD and VPP pins back to 5 V. (16) Turn off the power. The following figure shows steps (2) to (12).
X repetitions Write Verify Additional write Address increment
VPP
VPP VDD
VDD + 1 VDD VDD
X1
D0/P40 to D3/P43 D4/P50 to D7/P53
Data input
Data output
Data input
MD0 (P30)
MD1 (P31) MD2 (P32) MD3 (P33)
31
PD75P3018
8.3 Program Memory Read Procedure The PD75P3018 can read program memory contents using the following procedure. (1) Pull unused pins to Vss through resistors. Set the X1 pin low. (2) Supply 5 V to the VDD and VPP pins. (3) Wait 10 s. (4) Select the zero-clear program memory address mode. (5) Supply 6 V to the VDD and 12.5 V to the VPP pins. (6) Select the program inhibit mode. (7) Select the verify mode. Apply four pulses to the X1 pin. Every four clock pulses will output the data stored in one address. (8) Select the program inhibit mode. (9) Select the zero-clear program memory address mode. (10) Return the VDD and VPP pins back to 5 V. (11) Turn off the power. The following figure shows steps (2) to (9).
VPP VPP VDD
VDD + 1 VDD VDD
X1
D0/P40 to D3/P43 D4/P50 to D7/P53
Data output
Data output
MD0 (P30)
MD1 (P31)
"L"
MD2 (P32)
MD3 (P33)
32
PD75P3018
8.4 One-time PROM Screening Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC. Therefore, NEC recommends that after the required data is written and the PROM is stored under the temperature and time conditions shown below, the PROM should be verified via a screening.
Storage temperature 125C Storage time 24 hours
33
PD75P3018
*
9. ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (TA = 25 C)
Parameter Supply voltage PROM supply voltage Input voltage Symbol VDD VPP VI1 VI2 Output voltage High-level output current VO IOH Per pin Total of all pins Low-level output current IOL Per pin Total of all pins Operating ambient temperature Storage temperature TA Tstg Other than ports 4 and 5 Ports 4 and 5 (During N-ch open drain) Conditions Ratings -0.3 to +7.0 -0.3 to +13.5 -0.3 to VDD + 0.3 -0.3 to +14 -0.3 to VDD + 0.3 -10 -30 30 220 -40 to +85 -65 to +150 Unit V V V V V mA mA mA mA C C
Caution If the absolute maximum rating of even one of the parameters is exceeded even momentarily, the quality of the product may be degraded. The absolute maximum ratings are therefore values which, when exceeded, can cause the product to be damaged. Be sure that these values are never exceeded when using the product. Capacitance (TA = 25 C, VDD = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO f = 1 MHz Unmeasured pins returned to 0 V Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF
34
PD75P3018
Main System Clock Oscillation Circuit Characteristics (TA = -40 to +85 C)
Resonator Ceramic resonator Recomended Constants VDD = 2.2 to 5.5 V
X1 X2
Parameter Oscillation frequency (fX) Note 1
Conditions
MIN. 1.0
TYP.
MAX. 6.0 Note 2
Unit MHz
C1 VDD
C2
Oscillation stabilization time Note 3
After VDD has reached MIN. value of oscillation voltage range 1.0
4
ms
Crystal resonator
VDD = 2.2 to 5.5 V
X1 X2
Oscillation frequency (fX) Note 1
6.0 Note 2
MHz
C1 VDD
C2
Oscillation stabilization time Note 3
VDD = 4.5 to 5.5 V
10 30
ms
External clock
VDD = 1.8 to 5.5 V
X1 X2
X1 input frequency (fX) Note 1
1.0
6.0 Note 2
MHz
X1 input high-/ low-level widths (tXH, tXL)
83.3
500
ns
Notes 1. The oscillation frequency and X1 input frequency shown above indicate characteristics of the oscillation circuit only. For the instruction execution time, refer to AC Characteristics. 2. When the supply voltage is 1.8 V VDD < 2.7 V and the oscillation frequency is 4.19 MHz < fX 6.0 MHz, do not select processor clock control register (PCC) = 0011 as the instruction execution time. If PCC = 0011, one machine cycle is less than 0.95 s, falling short of the rated value of 0.95 s. 3. The oscillation stabilization time is the time required for oscillation to be stabilized after VDD has been applied or STOP mode has been released. Caution When using the main system clock oscillation circuit, wire the portion enclosed in the broken line in the above figure as follows to prevent adverse influences due to wiring capacitance: * Keep the wiring length as short as possible. * Do not cross the wiring with other signal lines. * Do not route the wiring in the vicinity of a line through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillation circuit at the same potential as VDD. * Do not ground to a power supply pattern through which a high current flows. * Do not extract signals from the oscillation circuit.
35
PD75P3018
Subsystem Clock Oscillation Circuit Characteristics (TA = -40 to +85 C, VDD = 2.2 to 5.5 V)
Resonator Crystal resonator
XT1 XT2 R C3 VDD C4
Recomended Constants
Parameter Oscillation frequency (fXT) Note 1
Conditions
MIN. 32
TYP. 32.768
MAX. 35
Unit kHz
Oscillation stabilization time Note 2
VDD = 4.5 to 5.5 V VDD 2.2 V
1.0
2 10
s
External clolck
XT1 input frequency (fXT) Note 1
32
100
kHz
XT1
XT2
XT1 input high-/ low-level widths (tXTH, tXTL)
5
15
s
Notes 1. The oscillation frequency and XT1 input frequency shown above indicate characteristics of the oscillation circuit only. For the instruction execution time, refer to AC Characteristics. 2. The oscillation stabilization time is the time required for oscillation to be stabilized after VDD has been applied. Caution When using the subsystem clock oscillation circuit, wire the portion enclosed in the broken line in the above figure as follows to prevent adverse influences due to wiring capacitance: * Keep the wiring length as short as possible. * Do not cross the wiring with other signal lines. * Do not route the wiring in the vicinity of a line through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillation circuit at the same potential as VDD. * Do not ground to a power supply pattern through which a high current flows. * Do not extract signals from the oscillation circuit. The subsystem clock oscillation circuit has a low amplification factor to reduce current dissipation and is more susceptible to noise than the main system clock oscillation circuit. Therefore, exercise utmost care in wiring the subsystem clock oscillation circuit.
36
PD75P3018
DC Characteristics (TA = -40 to +85 C, VDD = 2.2 to 5.5 V)
Parameter Low-level output current High-level input voltage VIH2 Ports 0, 1, 6, 7, RESET VIH1 Symbol IOL Per pin Total of all pins Ports 2, 3 2.7 V VDD 5.5 V 2.2 V VDD < 2.7 V 2.7 V VDD 5.5 V 2.2 V VDD < 2.7 V VIH3 Ports 4, 5 (During N-ch open drain) VIH4 Low-level input voltage VIL2 Ports 0, 1, 6, 7, RESET VIL1 X1, XT1 Ports 2, 3, 4, 5 2.7 V VDD 5.5 V 2.2 V VDD < 2.7 V 2.7 V VDD 5.5 V 2.2 V VDD < 2.7 V VIL3 High-level output voltage Low-level output voltage VOL1 VOH X1, XT1 SCK, SO/SB0, SB1, Ports 2, 3, 6, 7, BP0 to 7 IOH = -1 mA SCK, SO, Ports 2, 3, 4, 5, 6, 7, BP0 to 7 IOL = 15 mA VDD = 4.5 to 5.5 V IOL = 1.6 mA VOL2 SB0, SB1 During N-ch open drain Pull-up resistor 1 k High-level input leakage current ILIH1 ILIH2 ILIH3 Low-level input leakage current ILIL1 ILIL2 ILIL3 VIN = 13 V VIN = 0 V VIN = VDD Pins other than X1, XT1 X1, XT1 Ports 4, 5 (During N-ch open drain) Pins other than X1, XT1, Ports 4, 5 X1, XT1 Ports 4, 5 (During N-ch open drain) When input instruction is executed High-level output leakage current Low-level output leakage current Internal pull-up resistor RL1 VIN = 0 V Ports 0, 1, 2, 3, 6, 7 (except P00 pin) 50 100 200 k ILOH1 ILOH2 ILOL VOUT = VDD VOUT = 13 V VOUT = 0 V VDD = 5.0 V VDD = 3.0 V -10 -3 3 20 20 -3 -20 -30 -27 -8 3 20 -3 0.4 0.2 VDD V V 0.2 2.0 V 2.7 V VDD 5.5 V 2.2 V VDD < 2.7 V 0.7 VDD 0.9 VDD 0.8 VDD 0.9 VDD 0.7 VDD 0.9 VDD VDD - 0.1 0 0 0 0 0 VDD - 0.5 Conditions MIN. TYP. MAX. 15 150 VDD VDD VDD VDD 13 13 VDD 0.3 VDD 0.1 VDD 0.2 VDD 0.1 VDD 0.1 Unit mA mA V V V V V V V V V V V V V
A A A A A A A A A A A
SCK, SO/SB0, SB1, Ports 2, 3, 6, 7 Ports 4, 5 (During N-ch open drain)
37
PD75P3018
DC Characteristics (TA = -40 to +85 C, VDD = 2.2 to 5.5 V)
Parameter Symbol VAC0 = 0 IO = 5 A VLCD0 = VLCD VLCD1 = VLCD 2/3 VLCD2 = VLCD 1/3 IO = 1 A 2.2 V - VLCD - VDD 0 0.2 V Conditions MIN. 2.2 0 TYP. MAX. VDD 0.2 Unit V V
LCD drive voltage VLCD LCD output voltage VODC deviation
Note 1
(common) LCD output voltage VODS deviation
Note 1
(segment) Supply current Note 2 IDD1 6.0 MHz Note 3 VDD = 5.0 V 10 % Note 4 crystal IDD2 oscillation VDD = 3.0 V 10 %
Note 5
3.7 0.73 0.92 0.30 2.7 0.57 0.90 0.28 42 37 42 39 39 8.5 5.8 8.5 3.5 3.5 0.05 0.02 TA = 25 C 0.02
11.0 2.2 2.6 0.9 8.0 1.7 2.5 0.8 126 110 84 117 78 25 17 17 12 7 10 5 3
mA mA mA mA mA mA mA mA
HALT VDD = 5.0 V 10 % VDD = 3.0 V 10 %
C1 = C2 = 22 pF mode IDD1
4.19 MHz Note 3 VDD = 5.0 V 10 % Note 4 crystal VDD = 3.0 V 10 % Note 5 HALT VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 3.0 V 10 %
IDD2
oscillation
C1 = C2 = 22 pF mode IDD3 32.768 kHz
Note 6
Low-
A A A A A A A A A A A A A
voltage VDD = 2.5 V 10 % mode
Note 7
crystal oscillation
VDD = 3.0 V, TA = 25 C VDD = 3.0 V 10 % VDD = 3.0 V, TA = 25 C VDD = 3.0 V 10 %
Low power dissipation mode Note 8
IDD4
HALT Lowmode
voltage VDD = 2.5 V 10 % mode Note 7 VDD = 3.0 V, TA = 25 C Low power VDD = 3.0 V 10 % dissipation mode Note 8 VDD = 3.0 V, TA = 25 C
IDD5
XT1 = 0 V Note 9 VDD = 5.0 V 10 % STOP mode VDD = 3.0 V 10 %
Notes 1. Voltage deviation is the difference between the ideal values (VLCDn ; n = 0, 1, 2) of the segment and common outputs and the output voltage. 2. The current flowing through the internal pull-up resistor is not included. 3. Including the case when the subsystem clock oscillates. 4. When the device operates in high-speed mode with the processor clock control register (PCC) set to 0011. 5. When the device operates in low-speed mode with PCC set to 0000. 6. When the device operates on the subsystem clock, with the system clock control register (SCC) set to 1001 and oscillation of the main system clock stopped. 7. When the sub-oscillation control register (SOS) is set to 0000. 8. When the SOS is set to 0010. 9. When the SOS is set to 0011.
38
PD75P3018
AC Characteristics (TA = -40 to +85 C, VDD = 2.2 to 5.5 V)
Parameter CPU clock cycle time Note 1 (minimum instruction execution time = 1 machine cycle) Symbol tCY Operation with Conditions When ceramic VDD = 2.7 to 5.5 V or crystal is used VDD = 2.2 to 5.5 V MIN. 0.67 0.85 0.67 0.95 114 122 TYP. MAX. 64 64 64 64 125 Unit
s s s s s
main system When external VDD = 2.7 to 5.5 V clock clock is used
Operation with subsystem clock TI0, TI1, TI2 input frequency fTI VDD = 2.7 to 5.5 V
0 0
1 275
MHz kHz
TI0, TI1, TI2 high-/low-level widths
tTIH, tTIL
VDD = 2.7 to 5.5 V
0.48 1.8 Note 2 10 10 10
s s s s s s
Interrupt input high-/low-level tINTH, tINTL INT0 widths INT1, 2, 4 KR0-7 RESET low-level width tRSL
Notes 1. The cycle time of the CPU clock (F) is determined by the oscillation frequency of the connected resonator (and external clock), the system clock control register (SCC), and processor clock control register (PCC). The figure on the right shows the
Cycle time tCY [s]
tCY vs VDD
70 64 60 6 5 4 3 Operation guaranteed range (with main system clock)
supply voltage VDD vs. cycle time tCY characteristics when the device operates with the main system clock. 2. 2tCY or 128/fX depending on the setting of the interrupt mode register (IM0).
2
1
0.5
0
1
2
3
4
5
6
Supply voltage VDD [V]
Remark
The shaded portion indicates the range when the external clock is used.
39
PD75P3018
Serial transfer operation 2-wire and 3-wire serial I/O modes (SCK ... internal clock output): (TA = -40 to +85 C, VDD = 2.2 to 5.5 V)
Parameter SCK cycle time Symbol tKCY1 Conditions VDD = 2.7 to 5.5 V MIN. 1300 3800 SCK high-/low-level widths tKL1, tKH1 VDD = 2.7 to 5.5 V tKCY1/2-50 tKCY1/2-150 SI
Note 1
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns
setup time (to SCK ) tSIK1
VDD = 2.7 to 5.5 V
150 500
SI
Note 1
hold time (from SCK ) tKSI1
VDD = 2.7 to 5.5 V
400 600
SCK O AE SO delay time
Note 1
output
tKSO1
RL = 1 k ,
Note 2
VDD = 2.7 to 5.5 V
0 0
250 1000
ns ns
CL = 100 pF
2-wire and 3-wire serial I/O modes (SCK ... external clock input): (TA = -40 to +85 C, VDD = 2.2 to 5.5 V)
Parameter SCK cycle time Symbol tKCY2 Conditions VDD = 2.7 to 5.5 V MIN. 800 3200 SCK high-/low-level widths tKL2, tKH2 VDD = 2.7 to 5.5 V 400 1600 SI
Note 1
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns
setup time (to SCK ) tSIK2
VDD = 2.7 to 5.5 V
100 150
SI Note 1 hold time (from SCK ) tKSI2
VDD = 2.7 to 5.5 V
400 600
SCK O AE SO Note 1 output delay time
tKSO2
RL = 1 k ,
Note 2
VDD = 2.7 to 5.5 V
0 0
300 1000
ns ns
CL = 100 pF
Notes 1. In 2-wire serial I/O mode, read SB0 or SB1 instead. 2. RL and CL respectively indicate the load resistance and load capacitance of the SO output line.
40
PD75P3018
SBI mode (SCK ... internal clock output (master)): (TA = -40 to +85 C, VDD = 2.2 to 5.5 V)
Parameter SCK cycle time Symbol tKCY3 Conditions VDD = 2.7 to 5.5 V MIN. 1300 3800 SCK high-/low-level widths tKL3, tKH3 VDD = 2.7 to 5.5 V tKCY3/2-50 tKCY3/2-150 SB0, 1 setup time (to SCK ) SB0, 1 hold time (from SCK ) tKSI3 SCK O AE SB0, 1 output delay time SCK AE SB0, 1 O SB0, 1 O AE SCK O SB0, 1 low-level width SB0, 1 high-level width tKSB tSBK tSBL tSBH tKSO3 RL = 1 k ,
Note
TYP.
MAX.
Unit ns ns ns ns ns ns ns
tSIK3
VDD = 2.7 to 5.5 V
150 500 tKCY3/2 VDD = 2.7 to 5.5 V 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1000
ns ns ns ns ns ns
CL = 100 pF
SBI mode (SCK ... external clock input (slave)): (TA = -40 to +85 C, VDD = 2.2 to 5.5 V)
Parameter SCK cycle time Symbol tKCY4 Conditions VDD = 2.7 to 5.5 V MIN. 800 3200 SCK high-/low-level widths tKL4, tKH4 VDD = 2.7 to 5.5 V 400 1600 SB0, 1 setup time (to SCK ) SB0, 1 hold time (from SCK ) tKSI4 SCK O AE SB0, 1 output delay time SCK AE SB0, 1 O SB0, 1 O AE SCK O SB0, 1 low-level width SB0, 1 high-level width tKSB tSBK tSBL tSBH tKSO4 RL = 1 k ,
Note
TYP.
MAX.
Unit ns ns ns ns ns ns ns
tSIK4
VDD = 2.7 to 5.5 V
100 150 tKCY4/2 VDD = 2.7 to 5.5 V 0 0 tKCY4 tKCY4 tKCY4 tKCY4 300 1000
ns ns ns ns ns ns
CL = 100 pF
Note RL and CL respectively indicate the load resistance and load capacitance of the SB0, 1 output line.
41
PD75P3018
AC Timing Test Points (except X1 and XT1 inputs)
VIH VIL Test points
VOH VOL
Clock Timing
1/fX tXL tXH VDD-0.1 V X1 input 0.1 V
1/fXT tXTL tXTH VDD-0.1 V XT1 input 0.1 V
TI0, TI1, TI2 Timing
1/fTI tTIL tTIH
TI0, TI1, TI2
42
PD75P3018
Serial Transfer Timing 3-wire Serial I/O Mode
tKCY1,2 tKL1,2 tKH1,2
SCK
tSIK1,2
tKSI1,2
SI
Input data
tKSO1,2
SO
Output data
2-wire Serial I/O Mode
tKCY1,2 tKL1,2 tKH1,2
SCK tSIK1,2 tKSI1,2
SB0, 1
tKSO1,2
43
PD75P3018
Serial Transfer Timing Bus Release Signal Transfer
tKCY3, 4 tKL3, 4 tKH3, 4
SCK tKSB tSBL tSBH tSBK tSIK3, 4 tKSI3, 4
SB0, 1
tKSO3, 4
Command Signal Transfer
tKCY3, 4 tKL3, 4 tKH3, 4
SCK tKSB tSBK tSIK3, 4 tKSI3, 4
SB0, 1
tKSO3, 4
Interrupt Input Timing
tINTL
tINTH
INT0,1,2,4 KR0-7
RESET Input Timing
tRSL
RESET
44
PD75P3018
Data retention characteristics of data memory in STOP mode and at low supply voltage (TA = -40 to +85 C)
Parameter Release signal setup time Oscillation stabilization wait time
Note 1
Symbol tSREL tWAIT
Conditions
MIN. 0
TYP.
MAX.
Unit
s
215/fX Note 2 ms ms
Released by RESET Released by interrupt request
Notes 1. The oscillation stabilization wait time is the time during which the CPU stops operating to prevent unstable operation when oscillation is started. 2. Set by the basic interval timer mode register (BTM). (Refer to the table below.)
Wait time BTM3 - - - - BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 fX = 4.19 MHz 0 1 1 1 fX = 6.0 MHz 220/fX (approx. 250 ms) 220/fX (approx. 175 ms) 217/fX (approx. 31.3 ms) 217/fX (approx. 21.8 ms) 215/fX (approx. 7.81 ms) 215/fX (approx. 5.46 ms) 213/fX (approx. 1.95 ms) 213/fX (approx. 1.37 ms)
Data Retention Timing (when STOP mode released by RESET)
Internal reset operation Oscillation stabilization wait time STOP mode Data retention mode Operation mode
VDD
VDDDR STOP instruction execution
tSREL
RESET
tWAIT
Data Retention Timing (standby release signal: when STOP mode released by interrupt signal)
Oscillation stabilization wait time STOP mode Data retention mode Operation mode
VDD
VDDDR STOP instruction execution
tSREL
Standby release signal (interrupt request) tWAIT
45
PD75P3018
DC Programming Characteristics (TA = 25 5 C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V)
Parameter Input voltage high Symbol VIH1 VIH2 Input voltage low VIL1 VIL2 Input leakage current Output voltage high Output voltage low VDD supply current VPP supply current ILI VOH VOL IDD IPP MD0 = VIL, MD1 = VIH Except X1, X2 X1, X2 Except X1, X2 X1, X2 VIN = VIL or VIH IOH = -1 mA IOL = 1.6 mA VDD - 1.0 0.4 30 30 Conditions MIN. 0.7 VDD VDD - 0.5 0 0 TYP. MAX. VDD VDD 0.3 VDD 0.4 10 Unit V V V V
A
V V mA mA
Cautions 1. Ensure that VPP does not exceed +13.5 V including overshoot. 2. VDD must be applied before VPP, and cut after VPP. AC Programming Characteristics (TA = 25 5 C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V)
Parameter Address setup time
Note 2
Symbol (to MD0O) tAS tM1S tDS tAH tDH tDF tVPS tVDS tPW tOPW tM0S tDV tM1H tM1R tPCR tXH, tXL fX tI tM3S tM3H tM3SR
Note 2 Note 2
Note 1 tAS tOES tDS tAH tDH tDF tVPS tVCS tPW tOPW tCES tDV tOEH tOR -- -- -- -- -- -- -- tACC tOH -- --
Conditions
MIN. 2 2 2 2 2 0 2 2 0.95 0.95 2
TYP.
MAX.
Unit
s s s s s
130 ns
MD1 setup time (to MD0O) Data setup time (to MD0O) Address hold time
Note 2
(from MD0)
Data hold time (from MD0) MD0AEData output float delay time VPP setup time (to MD3) VDD setup time (to MD3) Initial program pulse width Additional program pulse width MD0 setup time (to MD1) MD0OAEData output delay time MD1 hold time (from MD0) MD1 recovery time (from MD0O) Program counter reset time X1 input high-/low-level width X1 input frequency Initial mode setting time MD3 setup time (to MD1) MD3 hold time (from MD1O) MD3 setup time (to MD0O) Data output delay time from address Data output hold time from address MD3 hold time (from MD0) MD3OAEData output float delay time
s s
1.0 1.05 21.0 ms ms
s
1
MD0 = MD1 = VIL tM1H + tM1R 50 s 2 2 10 0.125
s s s s s
4.19 2 2 2 Program memory read Program memory read Program memory read Program memory read Program memory read 0 2 2 2 2 130
MHz
s s s s s s s s
tDAD tHAD tM3HR tDFR
Notes 1. Symbol of corresponding PD27C256A 2. The internal address signal is incremented by 1 on the 4th rise of the X1 input, and is not connected to a pin.
46
PD75P3018
Program Memory Write Timing
tVPS VPP VPP VDD tVDS VDD+1 VDD VDD X1 tXL Data Input tI MD0 tPW MD1 tPCR MD2 tM3S MD3 tM3H tM1S tM1H tM1R tM0S tOPW tDS tOH tDV tDF Data Output Data Input tDS tDH tAH tAS Data Input tXH
P40-P43 P50-P53
Program Memory Read Timing
tVPS VPP VPP VDD tVDS VDD+1 VDD VDD X1 tXL tHAD P40-P43 P50-P53 tI MD0 tDV tM3HR Data Output Data Output tDFR tDAD tXH
MD1
tPCR MD2 tM3SR MD3
47
PD75P3018
10. PACKAGE DRAWINGS
80 PIN PLASTIC QFP ( 14)
A B
60 61
41 40 detail of lead end
D
C
S
80 1
21 20
F
G
H
IM
J K
P
N
L S80GC-65-3B9-3
NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q S
MILLIMETERS 17.2 0.4 14.0 0.2 14.0 0.2 17.2 0.4 0.8 0.8 0.30 0.10 0.13 0.65 (T.P.) 1.6 0.2 0.8 0.2 0.15+0.10 -0.05 0.10 2.7 0.1 0.1 3.0 MAX.
M
INCHES 0.677 0.016 0.551+0.009 -0.008 0.551+0.009 -0.008 0.677 0.016 0.031 0.031 0.012+0.004 -0.005 0.005 0.026 (T.P.) 0.063 0.008 0.031+0.009 -0.008 0.006+0.004 -0.003 0.004 0.106 0.004 0.004 0.119 MAX.
48
55
Q
PD75P3018
80 PIN PLASTIC TQFP (FINE PITCH) (
A B
12)
60 61
41 40
detail of lead end
C
D
S Q
80
21 1 20
F
G
H
I
M
J
K
P
N L
NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 14.00.2 12.00.2 12.00.2 14.00.2 1.25 1.25 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.145 +0.055 -0.045 0.10 1.05 0.050.05 55 1.27 MAX. INCHES 0.551 +0.009 -0.008 0.472 +0.009 -0.008 0.472 +0.009 -0.008 0.551 +0.009 -0.008 0.049 0.049 0.0090.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.0060.002 0.004 0.041 0.0020.002 55 0.050 MAX. P80GK-50-BE9-4
M
R
49
PD75P3018
*
11. RECOMMENDED SOLDERING CONDITIONS
Solder the PD75P3018 under the following recommended conditions. For the details on the recommended soldering conditions, refer to Information Document Semiconductor Device Mounting Technology Manual (C10535E). For the soldering methods and conditions other than those recommended, consult NEC. Table 11-1. Soldering Conditions of Surface Mount Type (1) PD75P3018GC-3B9: 80-pin plastic QFP (14 14 mm)
Soldering Method Infrared reflow VPS Wave soldering
Soldering Conditions Package peak temperature: 235 C, Time: 30 seconds max. (210 C min.), Number of times: 3 max. Package peak temperature: 215 C, Time: 40 seconds max. (200 C min.), Number of times: 3 max. Solder temperature: 260 C max., Time: 10 seconds max., Number of times: 1 Preheating temperature: 120 C max. (package surface temperature) Pin temperature: 300 C max., Time: 3 seconds max. (per side of device)
Symbol IR35-00-3 VP15-00-3 WS60-00-1
Pin partial heating
--
Caution Do not use two or more soldering methods in combination (except the pin partial heating method). (2) PD75P3018GK-BE9: 80-pin plastic TQFP (fine pitch) (12 12 mm)
Soldering Method Infrared reflow
Soldering Conditions
Symbol
Package peak temperature: 235 C, Time: 30 seconds max. (210 C min.), IR35-107-2 Number of times: 2 max., Exposure limit: 7 days Note (After that, prebaking is necessary at 125 C for 10 hours.) Package peak temperature: 215 C, Time: 40 seconds max. (200 C min.), VP15-107-2 Number of times: 2 max., Exposure limit: 7 days Note (After that, prebaking is necessary at 125 C for 10 hours.) WS60-107-1 Solder temperature: 260 C max., Time: 10 seconds max., Number of times: 1, Preheating temperature: 120 C max. (package surface temperature) Exposure limit: 7 days Note (After that, prebaking is necessary at 125 C for 10 hours.) Pin temperature: 300 C max., Time: 3 seconds max. (per side of device) --
VPS
Wave soldering
Pin partial heating
Note The number of days for storage after the dry pack has been opened. The storage conditions are 25 C, 65 % RH max. Caution Do not use two or more soldering methods in combination (except the pin partial heating method).
50
PD75P3018
APPENDIX A PD75316B, 753017 AND 75P3018 FUNCTION LIST
Parameter Program memory
PD75316B
Mask ROM 0000H-3F7FH (16256 8 bits) 000H-3FFH (1024 4 bits) 75X Standard
PD753017
Mask ROM 0000H-5FFFH (24576 8 bits)
PD75P3018
One-time PROM 0000H-7FFFH (32768 8 bits)
Data memory CPU Instruction execution time When main system clock is selected When subsystem clock is selected Pin connection 29 to 32 34 to 37 44 47 48 50 to 53 57 Stack SBS register Stack area Subroutine call instruction stack operation Instruction BRA !addr1 CALLA !addr1 MOVT XA, @BCDE MOVT XA, @BCXA BR BCDE BR BCXA CALL !addr CALLF !faddr Mask option Timer
75XL CPU * 0.95, 1.91, 3.81, or 15.3 s (at 4.19 MHz operation) * 0.67, 1.33, 2.67, or 10.7 s (at 6.0 MHz operation)
0.95, 1.91, or 15.3 s (at 4.19 MHz operation)
122 s (at 32.768 kHz operation) P40 to P43 P50 to P53 P12/INT2 P21 P22/PCL P30 to P33 IC None 000H-0FFH 2-byte stack Unavailable P12/INT2/TI1/TI2 P21/PTO1 P22/PCL/PTO2 P30/MD0 to P33/MD3 VPP SBS.3 = 1; Mk I mode selection SBS.3 = 0; Mk II mode selection n00H-nFFH (n = 0-3) Mk I mode: 2-byte stack Mk II mode: 3-byte stack Mk I mode: unavailable Mk II mode: available Available P40/D0 to P43/D3 P50/D4 to P53/D7
3 machine cycles 2 machine cycles Yes 3 channels: * Basic interval timer : 1 channel * 8-bit timer/event counter : 1 channel * Watch timer: 1 channel
Mk I mode: 3 machine cycles, Mk II mode: 4 machine cycles Mk I mode: 2 machine cycles, Mk II mode: 3 machine cycles None 5 channels: * Basic interval timer/watchdog timer: 1 channel * 8-bit timer/event counter: 3 channels (can be used as 16-bit timer/event counter) * Watch timer: 1 channel
51
PD75P3018
Parameter Clock output (PCL)
PD75316B
F, 524, 262, 65.5 kHz (Main system clock: at 4.19 MHz operation) 2 kHz (Main system clock: at 4.19 MHz operation)
PD753017
PD75P3018
* F, 524, 262, 65.5 kHz (Main system clock: at 4.19 MHz operation) * F, 750, 375, 93.8 kHz (Main system clock: at 6.0 MHz operation) * 2, 4, 32 kHz (Main system clock: at 4.19 MHz operation or subsystem clock: at 32.768 kHz operation) * 2.86, 5.72, 45.8 kHz (Main system clock: at 6.0 MHz operation)
BUZ output (BUZ)
Serial interface
3 modes are available * 3-wire serial I/O mode ... MSB/LSB can be selected for transfer top bit * 2-wire serial I/O mode * SBI mode Feedback resistor cut flag (SOS.0) Sub-oscillator current cut flag (SOS.1) None None None No External: 3, Internal: 3 VDD = 2.0 to 6.0 V TA = -40 to +85 C * 80-pin plastic TQFP (fine pitch) (12 x 12 mm) * 80-pin plastic QFP (14 x 14 mm) Provided Provided Yes Yes External: 3, Internal: 5 VDD = 2.2 to 5.5 V
SOS register
Register bank selection register (RBS) Standby release by INT0 Vectored interrupt
*
Supply voltage Operating ambient temperature Package
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PD75P3018
APPENDIX B DEVELOPMENT TOOLS
The following development tools have been provided for system development using the PD75P3018. In the 75XL Series, the relocatable assembler common to series is used in combination with the device file of each type.
RA75X relocatable assembler Host machine OS PC-9800 Series MS-DOS
TM
Part No. (name) Supply medium 3.5" 2HD 5" 2HD 3.5" 2HC 5" 2HC S5A13RA75X S5A10RA75X S7B13RA75X S7B10RA75X
Ver.3.30 to Ver.6.2 Note IBM PC/ATTM or compatible Refer to "OS for IBM PCs"
* *
Device file
Host machine OS PC-9800 Series MS-DOS Ver.3.30 to Ver.6.2 Note IBM PC/AT or compatible Refer to "OS for IBM PCs" Supply medium 3.5" 2HD 5" 2HD 3.5" 2HC 5" 2HC
Part No. (name)
S5A13DF753017 S5A10DF753017 S7B13DF753017 S7B10DF753017
Note Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function. Remark Operation of the assembler and device file is guaranteed only when using the host machine and OS described above.
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PD75P3018
PROM Write Tools
Hardware PG-1500 This is a PROM programmer that can program single-chip microcontroller with PROM in stand alone mode or under control of host machine when connected with supplied accessory board and optional programmer adapter. It can also program typical PROMs in capacities ranging from 256 K to 4 M bits. This is a PROM programmer adapter for the PD75P316BGC and PD75P3018GC. It can be used when connected to a PG-1500. This is a PROM programmer adapter for the PD75P316BGK and PD75P3018GK. It can be used when connected to a PG-1500. Connects PG-1500 to host machine with serial and parallel interface and controls PG-1500 on host machine. Host machine OS PC-9800 Series MS-DOS Ver.3.30 to Ver.6.2 Note IBM PC/AT or compatible Refer to "OS for IBM PCs" Supply medium 3.5" 2HD 5" 2HD 3.5" 2HD 5" 2HC S5A13PG1500 S5A10PG1500 S7B13PG1500 S7B10PG1500 Part No. (name)
PA-75P316BGC PA-75P316BGK Software PG-1500 controller
* *
Remark
Note Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function. Operation of the PG-1500 controller is guaranteed only when using the host machine and OS described above.
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PD75P3018
Debugging Tools In-circuit emulators (IE-75000-R and IE-75001-R) are provided as program debugging tools for the PD75P3018. Various system configurations using these in-circuit emulators are listed below.
Hardware IE-75000-R Note
1
The IE-75000-R is an in-circuit emulator to be used for hardware and software debugging during development of application systems using the 75X or 75XL Series products. For development of the PD75P3018, the IE-75000-R is used with optional emulation board (IE75300-R-EM) and emulation probe (EP-753018GC-R or EP-753018GK-R). Highly efficient debugging can be performed when connected to host machine and PROM programmer. The IE-75000-R includes a connected emulation board (IE-75000-R-EM). The IE-75001-R is an in-circuit emulator to be used for hardware and software debugging during development of application systems using the 75X or 75XL Series products. The IE-75001-R is used with optional emulation board (IE-75300-R-EM) and emulation probe (EP-753018GC-R or EP-753018GK-R). Highly efficient debugging can be performed when connected to host machine and PROM programmer.
2
IE-75001-R
IE-75300-R-EM Note EP-753018GC-R
This is an emulation board for evaluating application systems using the PD75P3018. It is used in combination with the IE-75000-R or IE-75001-R. This is an emulation probe for the PD75P3018GC. When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM. It includes a 80-pin conversion socket (EV-9200GC-80) to facilitate connections with target system. This is an emulation probe for the PD75P3018GK. When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM. It includes a 80-pin conversion adapter (EV-9500GK-80) to facilitate connections with target system. This program can control the IE-75000-R or IE-75001-R on a host machine when connected to the IE-75000-R or IE-75001-R via an RS-232-C or Centronics interface. Host machine OS PC-9800 Series MS-DOS Ver.3.30 to Ver.6.2 Note 3 IBM PC/AT or compatible Refer to "OS for IBM PCs" Supply medium 3.5" 2HD 5" 2HD 3.5" 2HC 5" 2HC S5A13IE75X S5A10IE75X S7B13IE75X S7B10IE75X Part No. (name)
EV-9200GC-80 EP-753018GK-R EV-9500GK-80 Software IE control program
*
Notes 1. This is a maintenance product. 2. The IE-75300-R-EM is sold separately. 3. Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function. Remark Operation of the IE control program is guaranteed only when using the host machine and OS described above.
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PD75P3018
OS for IBM PCs The following operating systems for the IBM PC are supported.
OS Version Ver.3.1 to Ver.6.3 Ver.5.0 to Ver.6.22 5.0/V to 6.2/V IBM DOS
TM
* * *
PC DOS
TM
MS-DOS
J5.02/V
Caution Ver. 5.0 or later includes a task swapping function, but this software is not able to use that function.
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PD75P3018
APPENDIX C RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Device Related Documents
Document No. Document Name Japanese English U10140E U10956E (This document)
*
PD753012, 753016, 753017 Data Sheet PD75P3018 Data Sheet
IC-9016 U10956J
PD753017 User's Manual PD753017 Instruction Table
75XL Series Selection Guide
U11282J IEM-5598 U10453J
IEU-1425 -- U10453E
Development Tool Related Documents
Document No. Document Name Japanese IE-75000-R/IE-75001-R User's Manual IE-75300-R-EM User's Manual Hardware EP-753017GC/GK-R User's Manual PG-1500 User's Manual RA75X Assembler Package User's Manual Software PG-1500 Controller User's Manual Operation Language PC-9800 Series (MS-DOS) base IBM PC Series (PC DOS) base EEU-967 EEU-651 EEU-731 EEU-730 EEU-704 EEU-5008 IEU-1495 EEU-1335 EEU-1346 EEU-1363 EEU-1291 U10540E EEU-846 U11354J English EEU-1416 EEU-1493
Other Related Documents
Document No. Document Name Japanese IC Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Devices Guide for Products Related to Microcomputer: Other Companies C10535J IEI-620 C10983J MEM-539 MEI-603 MEI-604 C10943X C10535E IEI-1209 C10983E -- MEI-1202 -- English
Caution The above related documents are subject to change without notice. For design purpose, etc., be sure to use the latest documents.
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PD75P3018
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
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PD75P3018
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Mountain View, California Tel: 800-366-9782 Fax: 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290
NEC Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
NEC Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH
Scandinavia Office Taeby Sweden Tel: 8-63 80 820 Fax: 8-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96. 3
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PD75P3018
MS-DOS is a trademark of Microsoft Corporation. IBM DOS, PC DOS, and PC/AT are trademarks of International Business Machines Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5
60

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